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| IS93C46B 1,024-BIT SERIAL ELECTRICALLY ERASABLE PROM FEATURES * Industry-standard Microwire Interface -- Non-volatile data storage -- Low voltage operation: Vcc = 2.5V to 5.5V -- Full TTL compatible inputs and outputs -- Auto increment for efficient data dump * x16 bit organization * Hardware and software write protection -- Defaults to write-disabled state at power-up -- Software instructions for write-enable/disable * Enhanced low voltage CMOS E2PROM technology * Versatile, easy-to-use Interface -- Self-timed programming cycle -- Automatic erase-before-write -- Programming status indicator -- Word and chip erasable -- Chip select enables power savings * Durable and reliable -- 40-year data retention after 1M write cycles -- 1 million write cycles -- Unlimited read cycles -- Schmitt-trigger inputs * Industrial and Automotive Temperature Grade ISSI JULY 2003 DESCRIPTION (R) The IS93C46B is a low-cost 1kb non-volatile, ISSI (R) serial EEPROM. It is fabricated using an enhanced CMOS design and process. The IS93C46B contains power-efficient read/write memory, and organization of 64 words of 16 bits. The IS93C46B is fully backward compatible with IS93C46. An instruction set defines the operation of the devices, including read, write, and mode-enable functions. To protect against inadvertent data modification, all erase and write instructions are accepted only while the device is write-enabled. A selected x16 word can be modified with a single WRITE or ERASE instruction. Additionally, the two instructions WRITE ALL or ERASE ALL can program the entire array. Once a device begins its self-timed program procedure, the data out pin (Dout) can indicate the READY/BUSY status by raising chip select (CS). The self-timed write cycle includes an automatic erase-before-write capability. The device can output any number of consecutive words using a single READ instruction. FUNCTIONAL BLOCK DIAGRAM DUMMY BIT R/W AMPS INSTRUCTION DECODE, CONTROL, AND CLOCK GENERATION ADDRESS REGISTER ADDRESS DECODER EEPROM ARRAY 64x16 DATA REGISTER DIN INSTRUCTION REGISTER DOUT CS SK WRITE ENABLE HIGH VOLTAGE GENERATOR Copyright (c) 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774 Rev. A 07/23/03 1 IS93C46B ISSI 8-Pin JEDEC SOIC "G" VCC NC NC GND (R) PIN CONFIGURATIONS 8-Pin DIP, 8-Pin TSSOP CS SK DIN DOUT 1 2 3 4 8 7 6 5 8-Pin JEDEC SOIC "GR" NC GND DOUT DIN NC VCC CS SK 1 2 3 4 8 7 6 5 CS SK DIN DOUT 1 2 3 4 8 7 6 5 VCC NC NC GND (Rotated) PIN DESCRIPTIONS CS SK DIN DOUT NC Vcc GND Chip Select Serial Data Clock Serial Data Input Serial Data Output Not Connected Power Ground instruction begins with a start bit of the logical "1" or HIGH. Following this are the opcode (2 bits), address field (6 bits), and data, if appropriate. The clock signal may be held stable at any moment to suspend the device at its last state, allowing clockspeed flexibility. Upon completion of bus communication, CS would be pulled LOW. The device then would enter Standby mode if no internal programming is underway. Read (READ) The READ instruction is the only instruction that outputs serial data on the DOUT pin. After the read instruction and address have been decoded, data is transferred from the selected memory register into a serial shift register. (Please note that one logical "0" bit precedes the actual 16-bit output data string.) The output on DOUT changes during the low-to-high transitions of SK (see Figure 3). Applications The IS93C46B is very popular in many high-volume applications which require low-power, low-density storage. Applications using this device include industrial controls, networking, and numerous other consumer electronics. Low Voltage Read The IS93C46B has been designed to ensure that data read operations are reliable in low voltage environments. They provide accurate operation with Vcc as low as 2.5V. Endurance and Data Retention The IS93C46B is designed for applications requiring up to 1M programming cycles (WRITE, WRALL, ERASE and ERAL). It provides 40 years of secure data retention without power after the execution of 1M programming cycles. Auto Increment Read Operations In the interest of memory transfer operation applications, the IS93C46B has been designed to output a continuous stream of memory content in response to a single read operation instruction. To utilize this function, the system asserts a read instruction specifying a start location address. Once the 16 bits of the addressed register have been clocked out, the data in consecutively higher address locations is output. The address will wrap around continuously with CS HIGH until the chip select (CS) control pin is brought LOW. This allows for single instruction data dumps to be executed with a minimum of firmware overhead. Device Operations The IS93C46B is controlled by a set of instructions which are clocked-in serially on the Din pin. Before each low-to-high transition of the clock (SK), the CS pin must have already been raised to HIGH, and the Din value must be stable at either LOW or HIGH. Each 2 Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774 Rev. A 07/23/03 IS93C46B ISSI Write All (WRALL) (R) Write Enable (WEN) The write enable (WEN) instruction must be executed before any device programming (WRITE, WRALL, ERASE, and ERAL) can be done. When Vcc is applied, this device powers up in the write disabled state. The device then remains in a write disabled state until a WEN instruction is executed. Thereafter, the device remains enabled until a WDS instruction is executed or until Vcc is removed. (See Figure 4.) (Note: Chip select must remain LOW until Vcc reaches its operational value.) The write all (WRALL) instruction programs all registers with the data pattern specified in the instruction. As with the WRITE instruction, the falling edge of CS must occur to initiate the self-timed programming cycle. If CS is then brought HIGH after a minimum wait of 250 ns (tCS), the DOUT pin indicates the READY/BUSY status of the chip (see Figure 6). Write Disable (WDS) The write disable (WDS) instruction disables all programming capabilities. This protects the entire device against accidental modification of data until a WEN instruction is executed. (When Vcc is applied, this part powers up in the write disabled state.) To protect data, a WDS instruction should be executed upon completion of each programming operation. Write (WRITE) The WRITE instruction includes 16 bits of data to be written into the specified register. After the last data bit has been applied to DIN, and before the next rising edge of SK, CS must be brought LOW. If the device is writeenabled, then the falling edge of CS initiates the selftimed programming cycle (see WEN). If CS is brought HIGH, after a minimum wait of 250 ns (5V operation) after the falling edge of CS (tCS) DOUT will indicate the READY/BUSY status of the chip. Logical "0" means programming is still in progress; logical "1" means the selected register has been written, and the part is ready for another instruction (see Figure 5). The READY/ BUSY status will not be available if: a) The CS input goes HIGH after the end of the self-timed programming cycle, tWP; or b) Simultaneously CS is HIGH, Din is HIGH, and SK goes HIGH, which clears the status flag. Erase Register (ERASE) After the erase instruction is entered, CS must be brought LOW. The falling edge of CS initiates the self-timed internal programming cycle. Bringing CS HIGH after a minimum of tCS, will cause DOUT to indicate the READ/BUSY status of the chip: a logical "0" indicates programming is still in progress; a logical "1" indicates the erase cycle is complete and the part is ready for another instruction (see Figure 8). Erase All (ERAL) Full chip erase is provided for ease of programming. Erasing the entire chip involves setting all bits in the entire memory array to a logical "1" (see Figure 9). INSTRUCTION SET - IS93C46B 16-bit Organization Address (1) Input Data (A5-A0) 11xxxx (A5-A0) 01xxxx 00xxxx (A5-A0) 10xxxx -- -- (D15-D0) (2) (D15-D0) (2) -- -- -- Instruction READ WEN (Write Enable) WRITE Start Bit 1 1 1 1 1 1 1 OP Code 10 00 01 00 00 11 00 WRALL (Write All Registers) WDS (Write Disable) ERASE ERAL (Erase All Registers) Notes: 1. x = Don't care bit. 2. If input data is not 16 bits exactly, the last 16 bits will be taken as input data. Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774 Rev. A 07/23/03 3 IS93C46B ISSI Value -0.3 to +6.5 -40 to +85 -40 to +125 -65 to +150 Unit V C C C (R) ABSOLUTE MAXIMUM RATINGS (1) Symbol VGND TBIAS TBIAS TSTG Parameter Voltage with Respect to GND Temperature Under Bias (Industrial) Temperature Under Bias (Automotive) Storage Temperature Notes: 1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. OPERATING RANGE Range Commercial Industrial Automotive Ambient Temperature 0C to +70C -40C to +85C -40C to +125C VCC 2.5V to 5.5V 2.5V to 5.5V 2.7V to 5.5V or 4.5V to 5.5V CAPACITANCE Symbol CIN COUT Parameter Input Capacitance Output Capacitance Conditions VIN = 0V VOUT = 0V Max. 5 5 Unit pF pF 4 Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774 Rev. A 07/23/03 IS93C46B ISSI Test Conditions IOL = 100 A IOL = 2.1 mA IOH = -100 A IOH = -400 A Vcc 2.5V to 5.5V 4.5V to 5.5V 2.5V to 5.5V 4.5V to 5.5V 2.5V to 5.5V 4.5V to 5.5V 2.5V to 5.5V 4.5V to 5.5V VIN = 0V to VCC (CS, SK,DIN,ORG) VOUT = 0V to VCC, CS = 0V Min. -- -- VCC - 0.2 2.4 0.7XVCC 0.7XVCC -0.3 -0.3 0 0 Max. 0.2 0.4 -- -- VCC+1 VCC+1 0.2XVCC 0.8 2.5 2.5 (R) DC ELECTRICAL CHARACTERISTICS TA = 0C to +70C for Commercial, -40C to +85C for Industrial, and -40C to +125C for Automotive. Symbol Parameter VOL VOL1 VOH VOH1 VIH VIL ILI ILO Notes: Automotive grade devices in this table are tested with Vcc = 2.7V to 5.5V and 4.5V to 5.5V. Unit V V V V V V A A Output LOW Voltage Output LOW Voltage Output HIGH Voltage Output HIGH Voltage Input HIGH Voltage Input LOW Voltage Input Leakage Output Leakage Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774 Rev. A 07/23/03 5 IS93C46B ISSI Test Conditions CS = VIH, SK = 1 MHz CMOS input levels CS = VIH, SK = 1 MHz CMOS input levels CS = VIH, SK = 0V Vcc 2.7V 5.0V 2.7V 5.0V 2.7V 5.0V Min. -- -- -- -- -- -- Max. 100 500 1 3 10 30 Unit A A mA mA A A (R) POWER SUPPLY CHARACTERISTICS TA = 0C to +70C for Commercial Symbol Parameter ICC1 ICC2 ISB Vcc Read Supply Current Vcc Write Supply Current Standby Current POWER SUPPLY CHARACTERISTICS TA = -40C to +85C for Industrial Symbol Parameter ICC1 ICC2 ISB Vcc Read Supply Current Vcc Write Supply Current Standby Current Test Conditions CS = VIH, SK = 1 MHz CMOS input levels CS = VIH, SK = 1 MHz CMOS input levels CS = VIH, SK = 0V Vcc 2.7V 5.0V 2.7V 5.0V 2.7V 5.0V Min. -- -- -- -- -- -- Max. 100 500 1 3 2 4 Unit A A mA mA A A POWER SUPPLY CHARACTERISTICS TA = -40C to +125C for Automotive Symbol Parameter ICC1 ICC2 ISB Vcc Read Supply Current Vcc Write Supply Current Standby Current Test Conditions CS = VIH, SK = 1 MHz CMOS input levels CS = VIH, SK = 1 MHz CMOS input levels CS = VIH, SK = 0V Vcc 2.7V 5.0V 2.7V 5.0V 2.7V 5.0V Min. -- -- -- -- -- -- Max. 100 500 1 3 3 8 Unit A A mA mA A A 6 Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774 Rev. A 07/23/03 IS93C46B ISSI Min. 0 0 0 500 350 250 500 350 250 500 250 250 100 50 50 100 100 100 0 0 0 100 100 100 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Max. 1 1 2 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 400 350 250 400 350 250 400 250 250 200 200 100 10 10 5 Unit Mhz Mhz Mhz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ms ms ms (R) AC ELECTRICAL CHARACTERISTICS TA = TA = 0C to +70C for Commercial, -40C to +85C for Industrial Symbol Parameter Test Conditions Vcc fSK tSKH tSKL tCS tCSS tDIS tCSH tDIH tPD1 tPD0 tSV tDF tWP SK Clock Frequency 2.5V to 5.5V 2.7V to 5.5V 4.5V to 5.5V 2.5V to 5.5V 2.7V to 5.5V 4.5V to 5.5V 2.5V to 5.5V 2.7V to 5.5V 4.5V to 5.5V 2.5V to 5.5V 2.7V to 5.5V 4.5V to 5.5V Relative to SK 2.5V to 5.5V 2.7V to 5.5V 4.5V to 5.5V 2.5V to 5.5V 2.7V to 5.5V 4.5V to 5.5V 2.5V to 5.5V 2.7V to 5.5V 4.5V to 5.5V 2.5V to 5.5V 2.7V to 5.5V 4.5V to 5.5V 2.5V to 5.5V 2.7V to 5.5V 4.5V to 5.5V 2.5V to 5.5V 2.7V to 5.5V 4.5V to 5.5V 2.5V to 5.5V 2.7V to 5.5V 4.5V to 5.5V 2.5V to 5.5V 2.7V to 5.5V 4.5V to 5.5V 2.5V to 5.5V 2.7V to 5.5V 4.5V to 5.5V SK HIGH Time SK LOW Time Minimum CS LOW Time CS Setup Time Din Setup Time Relative to SK CS Hold Time Relative to SK Din Hold Time Relative to SK Output Delay to "1" AC Test Output Delay to "0" AC Test CS to Status Valid AC Test CS to Dout in 3-state AC Test, CS=VIL Write Cycle Time Notes: 1. C L = 100pF Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774 Rev. A 07/23/03 7 IS93C46B ISSI Test Conditions Vcc 2.7V to 5.5V 4.5V to 5.5V 2.7V to 5.5V 4.5V to 5.5V 2.7V to 5.5V 4.5V to 5.5V 2.7V to 5.5V 4.5V to 5.5V Relative to SK Relative to SK Relative to SK Relative to SK AC Test AC Test AC Test AC Test, CS=VIL 2.7V to 5.5V 4.5V to 5.5V 2.7V to 5.5V 4.5V to 5.5V 2.7V to 5.5V 4.5V to 5.5V 2.7V to 5.5V 4.5V to 5.5V 2.7V to 5.5V 4.5V to 5.5V 2.7V to 5.5V 4.5V to 5.5V 2.7V to 5.5V 4.5V to 5.5V 2.7V to 5.5V 4.5V to 5.5V 2.7V to 5.5V 4.5V to 5.5V Min. 0 0 500 250 500 250 250 250 100 50 100 100 0 0 100 100 -- -- -- -- -- -- -- -- -- -- Max. 1 2 -- -- -- -- -- -- -- -- -- -- -- -- -- -- 400 250 400 250 250 250 200 100 10 5 Unit Mhz Mhz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ms ms (R) AC ELECTRICAL CHARACTERISTICS TA = -40C to +125C for Automotive Symbol Parameter fSK tSKH tSKL tCS tCSS tDIS tCSH tDIH tPD1 tPD0 tSV tDF tWP SK Clock Frequency SK HIGH Time SK LOW Time Minimum CS LOW Time CS Setup Time Din Setup Time CS Hold Time Din Hold Time Output Delay to "1" Output Delay to "0" CS to Status Valid CS to Dout in 3-state Write Cycle Time Notes: 1. C L = 100pF 8 Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774 Rev. A 07/23/03 IS93C46B ISSI SYNCHRONOUS DATA TIMING CS tCSS SK tDIS DIN tPD0 tPD1 tDF tDIH tSKH (R) AC WAVEFORMS FIGURE 2. T tSKL tCSH DOUT (READ) tSV DOUT (WRITE) (WRALL) (ERASE) (ERAL) STATUS VALID tDF FIGURE 3. READ CYCLE TIMING tCS CS 1 1 0 An A0 DIN DOUT 0 Dm D0 * *Address Pointer Cycles to the Next Register Notes: To determine address bits An-A0 and data bits Dm-Do, see Instruction Set. Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774 Rev. A 07/23/03 9 IS93C46B ISSI WRITE ENABLE (WEN) TIMING (R) AC WAVEFORMS FIGURE 4. tCS CS DIN 1 0 0 1 1 DOUT = 3-state FIGURE 5. WRITE (WRITE) CYCLE TIMING tCS CS DIN 1 0 1 An A0 Dm D0 tSV tDF READY DOUT BUSY tWP Notes: 1. After the completion of the instruction (DOUT is in READY status) then it may perform another instruction. If device is in BUSY status (DOUT indicates BUSY status) then attempting to perform another instruction could cause device malfunction. 2. To determine address bits An-A0 and data bits Dm-D0, see Instruction Set. 10 Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774 Rev. A 07/23/03 IS93C46B ISSI WRITE ALL (WRALL) TIMING (R) AC WAVEFORMS FIGURE 6. tCS CS 1 0 0 0 1 Dm D0 DIN tSV DOUT BUSY READY tWP Notes: 1. After the completion of the instruction (DOUT is in READY status) then it may perform another instruction. If device is in BUSY status (DOUT indicates BUSY status) then attempting to perform another instruction could cause device malfunction. 2. To determine data bits Dm-D0, see Instruction Set. FIGURE 7. WRITE DISABLE (WDS) CYCLE TIMING tCS CS DIN 1 0 0 0 0 DOUT = 3-STATE Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774 Rev. A 07/23/03 11 IS93C46B ISSI ERASE (REGISTER ERASE) CYCLE TIMING (R) AC WAVEFORMS FIGURE 8. tCS CS DIN 1 1 1 An An-1 A0 tSV DOUT BUSY READY tDF tWP Notes: To determine data bits An - A0, see Instruction Set. FIGURE 9. ERASE ALL (ERAL) CYCLE TIMING tCS CS DIN 1 0 0 1 0 tSV tDF READY DOUT BUSY tWP Note for Figures 8 and 9: After the completion of the instruction (DOUT is in READY status) then it may perform another instruction. If device is in BUSY status (DOUT indicates BUSY status) then attempting to perform another instruction could cause device malfunction. 12 Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774 Rev. A 07/23/03 IS93C46B ISSI Voltage Range 2.5V to 5.5V Order Part No. IS93C46B-3P IS93C46B-3G IS93C46B-3GR IS93C46B-3Z Package 300-mil Plastic DIP SOIC (rotated) JEDEC SOIC JEDEC 169-mil TSSOP (R) ORDERING INFORMATION Commercial: 0C to +70C Speed 1Mhz * ORDERING INFORMATION Industrial Range: -40C to +85C Speed 1Mhz * Voltage Range 2.5V to 5.5V Order Part No. IS93C46B-3PI IS93C46B-3GI IS93C46B-3GRI IS93C46B-3ZI Package 300-mil Plastic DIP SOIC (rotated) JEDEC SOIC JEDEC 169-mil TSSOP ORDERING INFORMATION Automotive Range: -40C to +125C Speed 1Mhz * Voltage Range 2.7V to 5.5V Order Part No. IS93C46B-3PA IS93C46B-3GRA Package 300-mil Plastic DIP SOIC JEDEC * The specification allows for higher speed. Please see the AC Charateristics for more information. Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774 Rev. A 07/23/03 13 |
Price & Availability of IS93C46B
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